中圖分類號：TN918.4 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.234186 中文引用格式： 賈旭光,，徐頌,，白海通，等. 基于FPGA的ZUC-256算法實現(xiàn)架構分析[J]. 電子技術應用,，2023，49(12)：45-49. 英文引用格式： Jia Xuguang,，Xu Song,，Bai Haitong，et al. Implementation and architecture analysis of ZUC-256 algorithm based on FPGA[J]. Application of Electronic Technique,，2023,，49(12)：45-49.
Implementation and architecture analysis of ZUC-256 algorithm based on FPGA
Jia Xuguang1，Xu Song2,，Bai Haitong3,，Deng Chao1
1.National Computer System Engineering Research Institute of China， Beijing 100083,， China,； 2.Intelligence Technology of CEC Co.，Ltd.,， Beijing 102209,， China；3.PLA Army,， Beijing 100044,， China
Abstract： The ZUC-256 algorithm architecture is analyzed，and a couple of implementation architectures suitable for FPGA are proposed for the multiple-input modulo 231-1 adder. By analyzing the critical path, various optimization schemes such as full hardware and hardware-software codesign are proposed, which can be applied to different application scenarios. Taking Zynq-7000 FPGA for example, the performance differences of each scheme are compared in detail. It has been verified that the proposed scheme can be applied to both ZUC-128 and ZUC-256 algorithms, and can be widely used in 4G LTE and 5G-NR mobile communication.
